MSX1FPGAカートリッジスロット追加

OCMを参考にしてMSX1FPGAにもカートリッジスロットを移植してみました。

http://caro.su/msx/ocm_de1.htm

PC-6001Fの音声出力とジョイスティック入力に対応したドーターボード(DEXT0)を利用します。

https://tms9918.booth.pm/

de1_top.vhd

（省略）
-- Generic top-level entity for Altera DE1 board
entity de1_top is
	generic (
		per_jt51_g				: boolean		:= true
	);
	port (
		-- Clocks
		clk50_i			: in    std_logic;
		clk27_i			: in    std_logic_vector( 1 downto 0);
		clk24_i			: in    std_logic_vector( 1 downto 0);
		clk_ext_i		: in    std_logic;
		-- MSX cartridge slot ports
		pSltClk     : out std_logic;	-- pCpuClk returns here, for Z80, etc.
		pSltRst_n   : in std_logic;		-- pCpuRst_n returns here
		bus_sltsl1_n_s : inout std_logic;
		bus_sltsl2_n_s : inout std_logic;
		bus_iorq_n_s  : inout std_logic;
		bus_rd_n_s    : inout std_logic;
		bus_wr_n_s    : inout std_logic;
		bus_addr_s  : inout std_logic_vector(15 downto 0);
		pSltDat     : inout std_logic_vector(7 downto 0);
		pSltBdir_n  : out std_logic;	-- Bus direction (not used in master mode)
		pSltCs1_n   : inout std_logic;
		pSltCs2_n   : inout std_logic;
		pSltCs12_n  : inout std_logic;
		pSltRfsh_n  : inout std_logic;
		pSltWait_n  : inout std_logic;
		pSltInt_n   : inout std_logic;
		bus_m1_n_s    : inout std_logic;
		bus_mreq_n_s  : inout std_logic;
		pSltRsv5    : out std_logic;            -- Reserved
		pSltRsv16   : out std_logic;            -- Reserved (w/ external pull-up)
		pSltSw1     : inout std_logic;          -- Reserved (w/ external pull-up)
		pSltSw2     : inout std_logic;          -- Reserved
（省略）
	-- Bus
--	signal bus_addr_s			: std_logic_vector(15 downto 0);
	signal bus_data_from_s	: std_logic_vector( 7 downto 0)		:= (others => '1');
	signal bus_data_to_s		: std_logic_vector( 7 downto 0);
--	signal bus_rd_n_s			: std_logic;
--	signal bus_wr_n_s			: std_logic;
--	signal bus_m1_n_s			: std_logic;
--	signal bus_iorq_n_s		: std_logic;
--	signal bus_mreq_n_s		: std_logic;
--	signal bus_sltsl1_n_s	: std_logic;
--	signal bus_sltsl2_n_s	: std_logic;
（省略）
--	ptjt: if per_jt51_g generate
		-- JT51 tests
--		jt51_cs_n_s <= '0' when bus_addr_s(7 downto 1) = "0010000" and bus_iorq_n_s = '0' and bus_m1_n_s = '1'	else '1';	-- 0x20 - 0x21

--		jt51: entity work.jt51_wrapper
--		port map (
--			clock_i			=> clock_3m_s,
--			reset_i			=> reset_s,
--			addr_i			=> bus_addr_s(0),
--			cs_n_i			=> jt51_cs_n_s,
--			wr_n_i			=> bus_wr_n_s,
--			rd_n_i			=> bus_rd_n_s,
--			data_i			=> bus_data_to_s,
--			data_o			=> bus_data_from_s,
--			ct1_o				=> open,
--			ct2_o				=> open,
--			irq_n_o			=> open,
--			p1_o				=> open,
			-- Low resolution output (same as real chip)
--			sample_o			=> open,
--			left_o			=> open,
--			right_o			=> open,
			-- Full resolution output
--			xleft_o			=> jt51_left_s,
--			xright_o			=> jt51_right_s,
			-- unsigned outputs for sigma delta converters, full resolution		
--			dacleft_o		=> open,
--			dacright_o		=> open
--		);
--	end generate;

	-- DEBUG
	D_display_s	<= bus_addr_s;
	pSltDat	<=  bus_data_to_s when (bus_wr_n_s = '0' and (bus_sltsl1_n_s	= '0' or bus_sltsl2_n_s	= '0')) else (others => 'Z');
	bus_data_from_s	<=  pSltDat;
--	pSltClk     : out std_logic;	-- pCpuClk returns here, for Z80, etc.
--	pSltRst_n   : in std_logic;		-- pCpuRst_n returns here
--	pSltRfsh_n  : inout std_logic;
--	pSltWait_n  : inout std_logic;
--	pSltInt_n   : inout std_logic;
	pSltBdir_n  <=	'1';
	pSltCs1_n   <=	bus_rd_n_s when( bus_addr_s(15 downto 14) = "01" and bus_mreq_n_s = '0' )else '1';
	pSltCs2_n   <=	bus_rd_n_s when( bus_addr_s(15 downto 14) = "10" and bus_mreq_n_s = '0' )else '1';
	pSltCs12_n  <=  pSltCs1_n and pSltCs2_n; 
	pSltRsv5    <= '1';
	pSltRsv16   <= '1';
	pSltSw1     <= '1';
	pSltSw2     <= '1';
（省略）