MSX1FPGAのSCC音源を無効にして、DCSG音源であるSN76489を移植してみました。
https://code.google.com/p/mist-board/source/browse/#svn%2Ftrunk%2Fcores%2Fsms%2Fsrc
基本的には既存のPSGを真似して、I/Oポート&H3F、&H7FにDCSGを実装するだけです。
(省略) signal psg_we_n_s: std_logic; (省略) psg_b : entity work.dcsg port map ( clk => clock_psg_en_i, WR_n => psg_we_n_s, D_in => d_from_cpu_s, outputs => audio_scc_o ); (省略) -- ESCCI escci: entity work.escci port map ( clock_i => clock_i, clock_en_i => clock_psg_en_i, reset_i => reset_i, -- addr_i => cpu_addr_s, data_i => d_from_cpu_s, data_o => d_from_mram_s, cs_i => mram_cs_s, rd_i => nrd_s, wr_i => nwr_s, -- ram_addr_o => mr_ram_addr_s, ram_data_i => ram_data_i, ram_ce_o => mr_ram_ce_s, ram_oe_o => open, ram_we_o => open, -- map_type_i => mr_type_s -- "-0" : SCC+, "01" : ASC8K, "11" : ASC16K -- Audio Out -- wave_o => audio_scc_o ); (省略) psg_we_n_s <= '0' when io_write_s = '1' and cpu_addr_s(5 downto 0) = "111111" else '1'; (省略) -- ESCCI mram_cs_s <= '0';
psg.vhd
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity dcsg is port ( clk : in STD_LOGIC; WR_n : in STD_LOGIC; D_in : in STD_LOGIC_VECTOR (7 downto 0); outputs : out signed(14 downto 0)); end entity; (省略) -- inst_dac: dac -- port map ( -- clk => clk, -- input => outputs, -- output => output ); process (clk) begin if rising_edge(clk) then clk_divide <= clk_divide+1; end if; end process; clk32 <= std_logic(clk_divide(3)); (省略) outputs <= "00" & signed(std_logic_vector( unsigned("00"&output0) + unsigned("00"&output1) + unsigned("00"&output2) + unsigned("00"&output3))) & "0000000"; end rtl;
プロジェクトには以下のファイルを追加します。
psg.vhd (← COMPONENTの名前をdcsgにリネームする) psg_noise.vhd psg_tone.vhd